There is no question that Artificial Intelligence continues to impact nearly all aspects of our lives.  System and chip development across all industries will be no exception, and in many ways stands to gain more than most.  Agentic-AI and systems of agents hold a great deal of promise, combined with advanced fundamental engines, to optimize and automate many aspects of chip and system development, with the potential to drive a new era of Intelligent System Design.  Dr. Cunningham will discuss the challenges of the chip and systems development markets, and provide insight into how agentic-ai, along with Cadence advanced engines, will provide the tools to meet those challenges and accelerate system design.

Performance is the primary driver in advanced packaging. Margins are low in many aspects. Achieving the best results requires carefully balancing factors such as signal integrity, power delivery, thermal management, mechanical and material properties, reliability, process control, yield, cycle time, cost, design for manufacturability (DFM), and overall system performance. This discussion examines the multi-physics aspects of advanced packaging—including electrical, mechanical, and thermal domains—and how these factors interact with one another.

In the artificial intelligence era, the industry's focus has long been on the race for faster compute. However, as AI models scale to trillions of parameters and real-time inference shifts from centralized data centers to the intelligent edge, the performance bottleneck is changing. The baton is now passing decisively to storage.

This keynote will explore the pivotal role of storage architecture in enabling the next wave of AI. In the data center, the massive, high-throughput demands of AI training require a fundamental rethink of storage solutions. It’s no longer just about capacity, but about delivering unprecedented, sustained bandwidth to keep expensive GPU resources fully utilized. This is the challenge that inspired our enterprise-grade MonTitan™ platform, a PCIe Gen5 SSD solution designed to feed the most demanding AI training and large language models.

Simultaneously, the explosion of AI-powered edge devices—from autonomous vehicles to factory robotics—requires a new class of storage that is fast, power-efficient, and incredibly reliable. We will journey from the core to the edge, examining the innovations in flash controllers and storage management that are critical for building a cohesive and performant AI infrastructure. Join us to discover how intelligent storage is no longer a passive component, but the active enabler driving the future of AI.

Practically project adopting Conformal ECO sometimes experience uncontrollable patch sizes. It is painful for users to dig out if this is tools issue or design issue. The ECO setup is like a tall wall outside the castle. Now we have a solution: SmartECO. It reduces setup effort, come out much more better path sizes than before. In this session, we will demonstrate how we integrate SmartECO into the Realtek flow.

SmartECO release setup cost and significantly reduce ECO patch size. Therefore, we can adopt SmartECO on larger and larger scope. In such condition, the more compact size are expected than before. Although SmartECO already creates very good quality ECO size, AI ECO which induce Cerebus and JedAI can further push the ECO patch quality to the limit. In this presentation, we will demonstrate how we integrate SmartECO and AI ECO into MediaTek s workflow and share our expectations for ECO. Presentation Takeaways : OnePass EC. Which benefit for both automation and manual ECO Induce SmartECO based on OnePass EC Push the limitation. AI ECO gain more eco size Future work and expectation.

In this presentation, we’ll introduce a couple of Cadence’s new digital design solutions to achieve intelligent chip design realization. These include early design exploration and analysis, chip design implementation by optimization AI applications with best productivity and QoR, and fast design closure from block to sub-system level. Building on this foundation of innovation, moving forward to next phase, we’ll also introduce Cadence latest development on agentic AI system to autonomous chip design era.

Early Detection, Early Treatment. Nowadays, there is a trend in advanced IC design to release products with tight schedules, high performance, and AI feature specifications. Over the past years, MediaTek has continuously upgraded the specifications of its flagship chip series - Dimensity. For example, the Dimensity 9400 improves performance by 28-40%, reduces power consumption by 40%, includes powerful AI features, and transitions from the N4 to N3 process compared to the Dimensity 9300. Overall, the Dimensity 9400 contains 30 billion transistors. A large number of transistors indicate a high current requirement to keep the chip functioning correctly, and process upgrades indicate increased metal resistance, both of which enlarge the risk of IR drop. High IR drop risk can cause chip function failures and degraded reliability. Typically, IR analysis in the full flow is performed at the signoff stage. If the IR drop violates specifications, it requires rolling back to the APR stage to adjust the circuit, involving numerous iterations to meet the target. If the APR stage still cannot directly reduce IR, it must be rolled back to the design level for changes, then rerun synthesis and APR stage, impacting schedules and specifications. Therefore, minimizing the risk of IR drop in early stage is crucial for saving the project schedules. In this presentation, we will discuss how to reduce the risk of IR drop in the synthesis stage to achieve earlier prediction and using design-level techniques to reduce IR drop risks. In our experiments, IR hotspots identified in the synthesis stage can map to 60% of the IR hotspot areas at the signoff level. Addressing these hotspots in the synthesis stage using design-level techniques can reduce the IR hotspot area by 53% in the synthesis stage.

Functional Safety is the essential requirement of automotive product that ensures the system free from unacceptable error during its operation. It is primarily governed by the standard ISO 26262. In physical implementation, it needs to meet the corresponding physical rules to ensure the component does not affect each other. Cadence uses USF (Unified Safety Format) as the specification to define functional safety requirements across all stage s tools. Innovus honors USF to guarantee the physical implementation fully meets ISO 26262 specification. In this presentation GUC shares the physical implementation experience in Automotive Functional Safety chip tape-outs, provides the overview of Innovus with USF practical experience. User can learn the overview of Automotive and Functional Safety, including part of the standard ISO 26262. GUC also shares their physical implementation experience at Automotive Functional Safety tape-outs, including Cadence USF flow overview, physical safety mechanism, and IR/EM experience on Automotive case.

As power integrity challenges continues to grow in advanced node designs, Voltus has introduced a suite of powerful updates to streamline analysis and improve user experience. This presentation provides an in-depth look at the latest enhancements in Voltus. We'll explore new features of Voltus InsightAI for easier IR hotspot debugging and fixing; signalEM XP flow which brings great improvement on performance especially with hyper-scale design; XUI, freshing new user interface that boosts productivity and accessibility. These innovations mark a significant step forward in making EMIR analysis more efficient, insightful and integrated.

With the increasing demand for computing power in AI applications, 3.5D SoIC stacking has emerged as one of the most promising options for optimized system performance and power efficiency. In the context of top-/bottom-die stacking, Power Delivery Network (PDN) optimization is crucial for enhancing system performance. In this presentation, we will share our experiences with key implementation strategies and PDN planning methodologies using Cadence Integrity 3D. Leveraging the Integrity 3D-IC platform, we successfully completed the SoIC test chip stacking N3P and N5 die in four months.

With the continuous advancement of AI technology, traditional 2D integrated circuits (2D ICs) can no longer meet the increasing demands for computing and bandwidth, as well as the shrinking size requirements. 3D integrated circuit (3D-IC) technology is a new design approach that achieves higher computing density, lower power consumption, and smaller size by stacking multiple chip layers. This paper marks a milestone as NovaTek's first 3D-IC tapeout. We introduce our experience using Integrity 3D-IC Floorplan, Auto Bump Synthesis, and high-bandwidth routing technology to complete chip implementation and pass internal signoff.   Cadence Integrity 3D-IC can fully support TSMC 3dblox 2.0, allowing users to describe 3DIC stacked architectures and inspect stacking results and quality through 3D Viewer. Additionally, Integrity 3D-IC can support interposer netlist creation and bump projection of interposer die, eliminating the need for users to prepare interposer netlist and interposer bump locations. This feature can significantly reduce the chip implementation timeline. Finally, we applied Integrity 3D-IC's high-bandwidth routing technology to HBM3e, conforming to HBM routing constraints and passing both PI and SI signoff results.

Chiplet-based architectures are transforming semiconductor design, offering scalability and efficiency—but also introducing new security challenges. This presentation explores how embedded security enclaves can enable trust propagation, cryptographic authentication, and post-quantum resilience across heterogeneous chiplet ecosystems. Through real-world examples, we highlight how Secure-IC supports secure integration, IP protection, and regulatory compliance, accelerating time to market while ensuring system integrity.

High-Level Synthesis (HLS) has been increasingly adopted in industry design flows due to its ability to deliver superior Quality of Results (QoR) compared to traditional handcrafted RTL methodologies. However, customer feedback indicates that the learning curve associated with new languages and toolsets can hinder broader adoption of Stratus HLS.

Cerebrus/Stratus leverages machine learning to automatically explore a wide range of RTL micro-architectures to meet Power, Performance, and Area (PPA) targets. This provides users with: 1) More automated and thorough micro-architecture exploration that would be impractical with handcrafted RTL methodologies, 2) Lowers the expertise required to perform micro-architecture exploration, and 3) Improved PPA outcomes.

Stratus AI further enhances this experience by integrating the capabilities of large language models (LLMs) to assist users not only in navigating Stratus HLS but also in generating codes. In this talk, we’ll show you the current state of our progress and what’s coming next.

HLS (High Level Synthesis) can produce high-quality PPA (performance, power and area) HDL designs, especially for signal processing algorithms and specialized AI workloads. However, HLS requires a designer to tune the quality of results by rewriting codes and selecting a set of HLS directives for a specific micro-architecture to meet the specifications, which requires manual efforts and repetitive synthesis process. In this talk, we discuss a more efficient HLS flow for with Large Language Model (LLM). The flow covers two major components in the synthesis process: front-end language wrapper and code transformation for optimization. The front-end wrapper translates a regular C/C++ codes into synthesizable codes. Then we apply code transformation to explore design candidates with different micro-architecture. In the preliminary experimental results, we collected a total of 755 software codes in C/C++. With GPT-4o, 348 codes successfully pass the code checking and fixing for synthesis. For the 348 C/C++ codes, 312 are correctly converted to HLS SystemC format and simulated at RTL to verify the results. Also, we demonstrated with a novel intermediate representation for more efficient design space exploration with micro-architecture.

Large Language Models (LLMs) have demonstrated impressive capabilities in zero-shot learning, contextual understanding, logical reasoning, and response generation. This talk introduces an innovative approach that leverages an LLM s in-context learning capability to automate hyperparameter tuning for VLSI placement. This approach employs a batch optimization mechanism to evaluate multiple hyperparameter configurations in parallel. Its effectiveness in improving placement quality, as measured by Half-Perimeter Wire Length (HPWL), is showcased through integration with academic placers across diverse placement scenarios and benchmark suites.

In recent years, Von Neuman Memory-Wall issues have lead the IMC (in memory computing) designs in ISSCC, JSSC and SOVC become the most mainstream. The memory wall is now the key bottleneck in edge AI interference chip design. The difference between NPU under Von Neuman architecture and IMC architecture is that the data calculation can be completed inside the memory, it can not only save external DRAM memory, but also save and reduce access power consumption. The reason for the vigorous development of CIM circuits is nothing more than the NN (neural network) or Transformer architecture, and the main operation inside the NN is the MAC operation. Because the calculation structure is simple, this operation can be put into the memory to greatly save memory access bandwidth. For the IMC design, it can be designed in digital, analog or hybrid manner or even heterogeneously integrated in high-bandwidth 3D environment. For various multi-function reconfigurable IMC chip design, Cadence StratusHLS tool makes it easier for IC designers to develop large and complex scale chips. For HB 3D environment integration, Cadence Sigrity and Clarity tools provide simulation and analysis platform required in the design process of 3D heterogeneous integrated chips.

•Use ML-driven Layout Generation with TSMC Advanced Node PDK for correct by construction design with various proposed result and scoring per design criteria

•Consider critical needs in advanced node analog design to meet DRC, LOD effect, ESD protection and reduce post trim insertion DRC and short issue

This report presents the MIAL (Mediatek Intelligent Automation Layout Tool) platform for analog device-level auto placement and user-defined placement, built on the Cadence DI, ADPR, and Modgen frameworks. We discuss its architecture and use in TSMC’s advanced process, highlighting its role in improving design efficiency and accuracy in advanced analog design.

A next‑generation integrated EM and RC extraction workflow for transmission‑line performance analysis. The approach delivers several key breakthroughs to reduce design effort and zero double-counting risk.

The analog design layout usually needs to do different processes porting and ECO. How to quickly and efficiently achieve these kinds of tasks becomes very important in the design cycle.

By using CADENCE ANIMATE automatic layout generation solution for the analog design flow, these kinds of tasks could be finished easily and smoothly. This tool can also generate a preliminary template layout of the analog design.

This experience sharing could let designers and layout engineers work on the analog design layout more convenient and save the total design turnaround time and efforts.

We’re exploring solutions for RC network analysis using DSPF data, focusing on key parasitic effects—layer capacitance, point-to-point resistance, and delay. By integrating Quantus Insight (QI) into Virtuoso analog design flows, we aim to improve accuracy and efficiency in post-layout (Spectre X) and EM/IR (Voltus-XFi) simulations. This approach helps boost design reliability, speed up convergence, and meet advanced node requirements

More information will be updated. Please stay tuned!

This presentation conducted a CFD simulation on a test area in a certain factory. This area uses a closed hot channel design and directs the hot air to the outside to improve the overall heat dissipation efficiency. The test cabinet uses a brush as a sealing material, which improves operational flexibility but also causes a higher heat leakage rate. The hot air in the hot channel is forced out by installing a fan. However, due to the large scale of the factory and the lengthy duct path, the fan exhaust efficiency is reduced, affecting the overall heat dissipation performance. This simulation effectively clarified the airflow bottleneck, providing a key basis for subsequent system adjustments and design optimization.

本案例針對某廠區測試區域進行CFD 熱流模擬分析，該區域採用封閉式熱通道設計，並將熱氣導引至室外，以提升整體散熱效率。測試機櫃使用毛刷作為封閉材質，雖提高了操作靈活性，但也造成較高的熱氣洩漏率。熱通道中的熱氣則透過加裝風扇進行強制排出。然而，由於廠區規模較大，風管路徑冗長，導致風扇抽風效率下降，影響整體排熱表現。透過本次模擬，有效釐清氣流瓶頸，為後續系統調整與設計優化提供關鍵依據。

This session introduces the transformative potential of data center digital twins in accelerating the design, simulation, and operation of next-generation AI factories. As modern data centers face challenges such as extreme GPU density, constrained power grids, and novel cooling technologies, traditional planning and operational methods are no longer sufficient.

Leveraging NVIDIA Omniverse, powered by OpenUSD and RTX technologies, alongside Cadence's digital twin solutions, this talk explores how developers and enterprises can build scalable, intelligent, and collaborative 3D workflows. We will showcase how OpenUSD unifies chiplet, PCB, rack, and infrastructure-level data into a shared, extensible digital twin environment, enabling simulation, optimization, and intelligent operation of data centers from design to deployment.

The briefing will also introduce Omniverse APIs, Kit-based development templates, and NIM microservices for generative AI, illustrating how the ecosystem accelerates both 3D application development and AI model integration in real-world data center operations.

This study utilizes Reality DC Simulation to conduct a comprehensive evaluation of future data center and facility designs, focusing on air-cooled and liquid-cooled infrastructure. The simulation enables modeling of cooling strategies and infrastructure components, including cooling towers, chillers, CRAH. By simulating various thermal loads and environmental conditions, the tool provides critical insights into system performance, energy efficiency, and equipment sizing. This approach supports informed decision-making in early-stage planning, ensuring optimal configuration of cooling infrastructure to meet future demands while minimizing operational costs and environmental impact.

For high power application in AI server, it needs power busbar to links with complex geometry. It is challenge to analyze with detail layout and busbar together. In this topic, it shares how to create the PI/Thermal model. And how do we use Cadence Celsius3D solver to run simulation to validate design before we sign off. Further, we also compare thermal aware PI result and it shows a significant difference compared to without thermal aware analysis.

The thermal behavior of integrated circuits (ICs) significantly impacts their performance. Generally, thermal conditions can be categorized into two types: transient and steady states, depending on whether time dependence is considered. In this presentation, we introduce simplified simulation model using Cadence Celsius. Furthermore, we integrate Python code to compile with the Cadence API to implement dynamic power control, enabling the investigation of IC thermal behavior and limitations. Finally, to support measurement and correlation, a physical test vehicle has been prepared for validation of results with Cadence Celsius.

With the rapid development of AI technology, the signal transmission speed required by AI servers is also increasing day by day, such as PCIE Gen6/Gen7, Ethernet 800G/1.6T, DDR6, etc., so the design of high-speed channels are becoming more and more challenging. Any effects that affect high-speed channels, such as impedance variation, insertion loss, crosstalk,  common-mode noise, interconnection effect, etc., will have a great impact on signal quality and cannot be ignored. To accurately consider these effects, it is necessary to use a 3D full-wave solver to solve the problems. However, when facing large-scale or multi-port cases, the time it takes to solve with a 3D solver is often time-consuming, so it is usually necessary to simplify the problem into several small problems to solve, but sometimes it may produce additional negative effects such as port impedance mismatch. Cadence Clarity 3D uses its unique technology to shorten the solution time, allowing designers to more immediately modify or optimize their high-speed channel designs to meet the time to market of customer products.

As memory Plan-Of-Record (POR) data rates continue to increase, achieving high-quality motherboard memory routing strategies becomes essential for rapid data transfer. To accelerate design transformation and automation for customers’ PCB design, Intel has partnered with Cadence to implement the significant business value of streamlining and automating customer memory board design processes through an automated memory simulation tool. This tool is proposed to accelerate simulation process, simplify manual setup steps, unify EDA tool environment setups, auto-generate report, schedule simulation task. It will greatly improve simulation time and work efficiency. Designers can leverage this tool to streamline the design process, moving resource to focus on achieving high-quality board design.

Broadening the adoption of hardware emulation with next generation emulation appliance

 

In the recent years, there has been significant growth in semiconductor design activity and forecasts indicate this trend to only increase in the future. RTL design and verification are key challenges in the semiconductor design cycle and acceleration via emulation has been predominant in the industry for decades, however, the adoption of this technology has primarily catered to the needs of large-scale ‘billion-gate’ class designs in recent years.

 

There are design teams that create IP or small-scale yet mission critical ASIC/SoC designs across organizations that strive to enable emulation to accelerate their D&V process but existing enterprise-based emulators in the industry are typically out of reach for these users due to a variety of reasons such as limited capital budget, low priority in resource allocation, or small companies that lack the data center infrastructure to house these large-scale emulators.

 

To reduce the barrier of adoption, Cadence is introducing a solution to address this market demand – Palladium Z3 System Studio. It is a stand-alone emulation appliance tailored for emulating designs of up to 128 million gates. In this session, we intend to present the benefits and solutions of Palladium Z3 System Studio, a leading-edge emulation appliance lowering the adoption barrier significantly for D&V teams to accelerate their hardware/software co-verification workloads.

 

Cache coherence is a critical issue in modern multi-core processor design, directly impacting system performance and reliability. This paper proposes a solution based on Portable Stimulus Standard (PSS) technology to optimize the cache coherence mechanism of MIPS CPUs. We employ Cadence Perspec as the EDA tool and integrate the vendor-provided coherence lib to achieve efficient and comprehensive verification. We detail the application methods of PSS technology, including scenario modeling, constraint definition, and test generation. By utilizing Cadence Perspec, we can flexibly generate complex verification scenarios and leverage the coherence lib to ensure the correctness and robustness of the cache coherence protocol. Practical validation demonstrates the significant advantages of PSS technology in improving verification coverage and reducing verification time. The results indicate that the combination of PSS technology, Cadence Perspec, and coherence lib can greatly reduce the effort required for cache coherence verification and provide reliable solutions. Since the coherence lib is based on ARM or RISC-V implementations and cannot be directly used in MIPS CPUs, we proposes modifications based on Cadence SML / coherence library to adapt the scenarios while preserving their main characteristics for MIPS CPU implementation. Our research provides valuable references for cache coherence verification across different architectures or instruction sets.

Skymizer specializes in AI-centric hardware and compiler design. In this talk, we share our experience using Cadence Palladium to verify our Language Processing Unit (LPU) and SoC integration. Initially, LPU simulations took days to complete; with Palladium, we reduced runtime to a few hours. We also applied this methodology to full-system and PCIe subsystem verification, benefiting from Cadence AE support to establish a robust verification flow. We’ll present our proposed methodology—including the PZ3L protocol layer—and compare compile/runtime metrics across FPGA, simulator, and Palladium. Notably, full language model inference (e.g., LLaMA) was unfeasible on traditional simulators but successfully executed on Palladium. This case highlights a scalable, practical path from RTL to system-level AI verification. 

Skymizer 專注於 AI 加速器與編譯技術的開發。本次分享將介紹我們如何透過 Cadence Palladium 完成 Language Processing Unit（LPU）與 SoC 的整合驗證。初期模擬需耗時數日，導入 Palladium 後大幅縮短至數小時。我們也將說明此方法如何擴展應用至系統層級與 PCIe 驗證流程，在 Cadence AE 協助下建立初步流程，包含 PZ3L 架構概述。簡報將比較 FPGA 與 Palladium 的編譯時間、模擬器與 Palladium 在執行語言模型（如 LLaMA）上的時效差異。Palladium 成功完成傳統模擬器無法執行的推論驗證，展示其對 AI 系統驗證的實用價值。

Design verification (DV) has evolved from traditional simulation-centric approaches into a comprehensive ecosystem that includes advanced simulation environments, fast-turnaround emulation, virtual platforms, and formal verification — forming the backbone of today’s cutting-edge SoC development. As system complexity continues to surge and time-to-market pressures intensify, the need for smarter, more adaptive verification strategies has never been more critical.

In this presentation, we will share GUC’s experience in building a robust and scalable DV flow using Cadence solutions, and explore the next frontier: integrating AI-augmented methodologies. Together, we will rethink and brainstorm how AI and machine learning can enhance coverage closure, accelerate debug, optimize regression strategies, and fundamentally transform the DV flow into a more intelligent, proactive, and efficient engine that drives future semiconductor innovation.

More details to be provided later! Please stay tuned!